Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2005-03-14
2009-02-17
Tran, Len (Department: 2616)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
C712S214000, C712S201000, C712S027000, C712S026000, C712S025000, C711S005000, C711S220000
Reexamination Certificate
active
07493469
ABSTRACT:
From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.
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Shichiku Ricardo T.
Yoshida Shin'ichi
Birch & Stewart Kolasch & Birch, LLP
Clark Maxwell A
Sharp Kabushiki Kaisha
Tran Len
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