Pipe scheduling for pipelines based on destination register...

Details Pipe scheduling for pipelines based on destination register... Pipe scheduling for pipelines based on destination register...

2009-07-01

2011-11-08

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S214000

Reexamination Certificate

active

08055883

ABSTRACT:
A data processing apparatus1has a plurality of registers10of the same type of register and a plurality of processing pipelines40, 50, each processing pipeline40, 50being arranged to process instructions. At least one instruction includes a destination register specifier specifying which of said registers is a destination register for storing a processing result of the at least one instruction. Instruction issuing circuitry26is configured to issue the at least one instruction for processing by one of the plurality of processing pipelines. The instruction issuing circuitry26selects the one of the plurality of processing pipelines to which the candidate instruction is issued in dependence upon the value of the destination register specifier of the candidate instruction.

REFERENCES:
patent: 5678016 (1997-10-01), Eisen et al.
patent: 6195744 (2001-02-01), Favor et al.
patent: 6219780 (2001-04-01), Lipasti
patent: 6944750 (2005-09-01), Sheaffer
patent: 2009/0260013 (2009-10-01), Heil et al.

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