Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2000-03-31
2003-07-22
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C710S262000, C712S229000
Reexamination Certificate
active
06598149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer systems and more specifically to enhancing performance when performing code transitions of data operating modes.
2. Description of the Related Art
In a computer system, a processor typically operates on data which is in one of several data modes, having different formats. For example, an execution unit of a processor may operate on integer data or it may operate on a floating point data. Generally, floating point operations are utilized when higher precision results are desired. Floating point data is represented in a different format than integer data.
Since integer and floating point operations utilize different data representations, in many state of the art processors, separate structures are allocated to execute integer and floating point instructions. This difference includes the use of separate registers for integer and floating point data. The operation of separate integer and floating units within a processor, as well as the execution of the floating point and integer instructions to operate on these types of data formats, are known in the art.
More recently, processors are designed to execute instructions which operate on another type of data format. This new type of data format is termed packed data. Instead of performing scalar operations, packed data operations are designed to operate on packed data. Although separate structures can be designed within a processor to perform the packed data operations, a more common practice is to alias packed data registers on floating point registers. That is, the floating point instructions and the packed data instructions at least appear to software to be executed on the same set of logical registers within a processor. A variety of techniques can be used to implement this aliasing scheme of floating point and packed data, and one such example is described in U.S. Pat. No. 5,835,748.
An example of a processor which implements aliasing of floating point and packed data is a processor within the Intel Architecture Family of Processors, which includes the Pentium® processor, manufactured by Intel Corporation of Santa Clara, Calif. In one particular approach, the floating point operating registers of the processor is also utilized to perform packed data operations. The same logical registers are utilized to perform both scalar floating point and packed data operations. The instructions that manipulate the two types of data in these registers are significantly different. The floating point instructions perform floating point scalar operations and packed data instructions perform packed data operations.
With the Intel Architecture Family described above, the aliasing requires the use of a special set of tags which correspond to data stored within the data registers. In the floating point mode, the tags are used to identify which of the registers contain a valid floating point word. When a floating point operation is to be executed, the processor enters into a floating point operative state in which the registers are treated as floating point registers for executing the instruction. However, when the processor operates in the packed data operative state, the data stored in the floating point registers must now conform to the operating parameters established for executing a packed data instruction. Since the data formats are different for packed data and floating point data formats, a typical practice is to implement a data flush and load new data when the operating mode switches between floating point and packed data operations.
This may not be a significant concern if the processor operates for an extended period of time in a given mode of operation before transitioning to the other mode. However, when a substantial amount of mixed mode operation is to be performed, the processor is forced to flush the data pipeline to switch from one format mode to another. This constant switching between modes results in significant processor time being wasted in continually reinitiating the registers to execute the different instruction set. The present invention describes one scheme in which performance is enhanced when such mixed mode operations are desired.
REFERENCES:
patent: 5255379 (1993-10-01), Melo
patent: 5835748 (1998-11-01), Orenstein et al.
patent: 6173394 (2001-01-01), Guttag et al.
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