Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2008-06-10
2008-06-10
Dollinger, Tonia L. M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S034000
Reexamination Certificate
active
07386704
ABSTRACT:
A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.
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Cherasaro Troy
Jackson Larry
Jones Mark
Rapp John W.
Schulz Kenneth R.
Dollinger Tonia L. M.
Graybeal Jackson Haley LLP
Lockheed Martin Corporation
Wurm Mark A.
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