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Operand and result forwarding between differently sized...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Operand cache addressed by the instruction address for reducing

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Operand file using pointers and reference counters and a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Operand queue for use in a floating point unit to reduce...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Operand queues for streaming data: A processor register file...

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Operating system device centric agent

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
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Operating system thread scheduling for optimal heat dissipation

Electrical computers and digital processing systems: processing – Processing control
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Operation frame filtering, building, and execution

Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
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Operation processing device, system and method having...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Operation, compare, branch VLIW processor

Electrical computers and digital processing systems: processing – Processing control – Branching
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Operation-processing apparatus

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Optimal redundant arithmetic for microprocessors design

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Optimization of a hardware resource shared by a multiprocessor

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
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Optimization of instruction stream execution that includes a...

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
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Optimized allocation of multi-pipeline executable and...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Optimized branch predictions for strongly predicted compiler...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Optimized storage system and method for a processor that execute

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Optimizing cache data load required for functions in loop...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Optimum power efficient shifting algorithm for schedulers

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Ordering scheme with architectural operation decomposed into...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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