Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2006-06-13
2006-06-13
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C711S141000, C712S023000, C712S216000
Reexamination Certificate
active
07062636
ABSTRACT:
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine The issue engine categorizes operations as at least one of either a speculative operation, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.
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Baxter Jeffery J.
Hammond Gary N.
Zaidi Nazar A.
Blakely , Sokoloff, Taylor & Zafman LLP
Kim Kenneth S.
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