Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2006-09-29
2009-12-01
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
active
07627739
ABSTRACT:
Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.
REFERENCES:
patent: 4484275 (1984-11-01), Katzman et al.
patent: 4639864 (1987-01-01), Katzman et al.
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 4672537 (1987-06-01), Katzman et al.
patent: 4751639 (1988-06-01), Corcoran et al.
patent: 4807116 (1989-02-01), Katzman et al.
patent: 4817091 (1989-03-01), Katzman et al.
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 4847755 (1989-07-01), Morrison et al.
patent: 4891787 (1990-01-01), Gifford
patent: 5084891 (1992-01-01), Ariyavisitakul et al.
patent: 5212777 (1993-05-01), Gove et al.
patent: 5475856 (1995-12-01), Kogge
patent: 5526313 (1996-06-01), Etoh et al.
patent: 5535405 (1996-07-01), Byers et al.
patent: 5691870 (1997-11-01), Gebara
patent: 5774736 (1998-06-01), Wright et al.
patent: 5966528 (1999-10-01), Wilkinson et al.
patent: 6021489 (2000-02-01), Poplingher
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6098030 (2000-08-01), McMinn
patent: 6199095 (2001-03-01), Robinson
patent: 6216236 (2001-04-01), Miyao et al.
patent: 6247118 (2001-06-01), Zumkehr et al.
patent: 6324643 (2001-11-01), Krishnan et al.
patent: 6374349 (2002-04-01), McFarling
patent: 6427206 (2002-07-01), Yeh et al.
patent: 6496056 (2002-12-01), Shoji
patent: 6625750 (2003-09-01), Duso et al.
patent: 6763452 (2004-07-01), Hohensee et al.
patent: 6766419 (2004-07-01), Zahir et al.
patent: 6877084 (2005-04-01), Christie
patent: 6924790 (2005-08-01), Bi
patent: 6954845 (2005-10-01), Arnold et al.
patent: 6954923 (2005-10-01), Yates, Jr. et al.
patent: 7093147 (2006-08-01), Farkas et al.
patent: 2001/0011346 (2001-08-01), Yoshimi
patent: 2001/0020267 (2001-09-01), Koino
patent: 2001/0021974 (2001-09-01), Lee
patent: 2001/0025338 (2001-09-01), Zumkehr et al.
patent: 2001/0032309 (2001-10-01), Henry et al.
patent: 2001/0047467 (2001-11-01), Yeh et al.
patent: 2002/0032718 (2002-03-01), Yates et al.
patent: 2002/0087828 (2002-07-01), Arimilli et al.
patent: 2002/0095666 (2002-07-01), Tabata et al.
patent: 2002/0112227 (2002-08-01), Kramskoy et al.
patent: 2002/0124196 (2002-09-01), Morrow et al.
patent: 2002/0144247 (2002-10-01), Tirumalai et al.
patent: 2002/0184385 (2002-12-01), Kato
patent: 2003/0005265 (2003-01-01), Barowski et al.
patent: 2003/0005419 (2003-01-01), Pieper et al.
patent: 2003/0074649 (2003-04-01), Poulsen et al.
patent: 2003/0079113 (2003-04-01), Nguyen et al.
patent: 2003/0101443 (2003-05-01), Kosche et al.
patent: 2003/0135771 (2003-07-01), Cupps et al.
patent: 2003/0200537 (2003-10-01), Barsness et al.
patent: 2003/0200539 (2003-10-01), Fu et al.
patent: 2004/0003309 (2004-01-01), Cai et al.
patent: 2004/0073894 (2004-04-01), Chen et al.
patent: 2004/0073899 (2004-04-01), Luk et al.
patent: 2004/0093591 (2004-05-01), Kalogeropulos et al.
patent: 2004/0103410 (2004-05-01), Sakai
patent: 2004/0153749 (2004-08-01), Schwarm et al.
patent: 2004/0174944 (2004-09-01), Uht
patent: 2004/0225871 (2004-11-01), Irie et al.
patent: 2005/0005203 (2005-01-01), Czajkowski
patent: 2005/0066153 (2005-03-01), Sharangpani et al.
patent: 2005/0086650 (2005-04-01), Yates, Jr. et al.
patent: 2005/0093607 (2005-05-01), Marshall et al.
patent: 2005/0132238 (2005-06-01), Nanja
patent: 2005/0138478 (2005-06-01), Safford et al.
patent: 2005/0149915 (2005-07-01), Wu et al.
patent: 2005/0155026 (2005-07-01), DeWitt, Jr. et al.
patent: 2005/0240814 (2005-10-01), Sasakura et al.
patent: 2005/0246613 (2005-11-01), Blaauw et al.
patent: 2006/0020838 (2006-01-01), Tschanz et al.
patent: 2006/0020852 (2006-01-01), Bernick et al.
patent: 2006/0101303 (2006-05-01), Bower, III et al.
patent: 2006/0181857 (2006-08-01), Belady et al.
patent: 2006/0202713 (2006-09-01), Shumarayev
patent: 2006/0202714 (2006-09-01), Hoang et al.
patent: 2006/0206882 (2006-09-01), Illowsky et al.
patent: 2006/0212753 (2006-09-01), Sato
patent: 2007/0006178 (2007-01-01), Tan
patent: 2007/0050555 (2007-03-01), Ferren et al.
patent: 2007/0050556 (2007-03-01), Ferren et al.
patent: 2007/0050557 (2007-03-01), Ferren et al.
patent: 2007/0050581 (2007-03-01), Mangione-Smith
patent: 2007/0050582 (2007-03-01), Mangione-Smith
patent: 2007/0050604 (2007-03-01), Ferren et al.
patent: 2007/0050605 (2007-03-01), Ferren et al.
patent: 2007/0050606 (2007-03-01), Ferren et al.
patent: 2007/0050607 (2007-03-01), Ferren et al.
patent: 2007/0050608 (2007-03-01), Ferren et al.
patent: 2007/0050609 (2007-03-01), Ferren et al.
patent: 2007/0050659 (2007-03-01), Ferren et al.
patent: 2007/0050660 (2007-03-01), Ferren et al.
patent: 2007/0050661 (2007-03-01), Ferren et al.
patent: 2007/0050672 (2007-03-01), Mangione-Smith
patent: 2007/0050775 (2007-03-01), Ferren et al.
patent: 2007/0050776 (2007-03-01), Ferren et al.
patent: 2007/0055848 (2007-03-01), Ferren et al.
patent: 2007/0067611 (2007-03-01), Ferren et al.
patent: 2007/0074173 (2007-03-01), Ferren et al.
Balasubramonian et al.; Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures; 2000; IEEE; pp. 1-13.
Shen et al.; Modern Processor Design: Fundamentals of Superscalar Processors; 2002; McGraw Hill; Beta Edition; p. 423.
Juan, Sanjeevan & Navarro; Dynamic History-Length Fitting: A third level of adaptivity for branch prediction; 1998, IEEE, pp. 155-166.
Chang, Po-Yung et al.; “Branch Classification: a New Mechanism for Improving Branch Prediction Performance”; International Journal of Parallel Programming; 1994; pp. 22-31; Ann Arbor, USA.
Kundu, Partha, et al.; “A Case for Shared Instruction Cache on Chip Multiprocessors running OLTP”; ACM SIGARCH Computer Architecture News; Jun. 2004; pp. 11-18; vol. 32, No. 3; ACM Press.
Rotenberg, Eric et al.; “Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching”; International Symposium on Microarchitecture; 1996; pp. 24-34; IEEE.
Sodani, Avinash et al.; “Dynamic Instruction Reuse”; ISCA; Jun. 1997; pp. 1- 12; ACM Press.
“Bayes' theorem”; Facts, Info and Encyclopedia article; pp. 1-6; located at: http://absoluteastronomy.com/encyclopedia/b/ba/bayes—theoreml.htm; printed on Aug. 27, 2005.
“Bayes' theorem”; Wikipedia, the free encyclopedia; pp. 1-6; located at: http://en.wikipedia.org/wiki/Bayes—theorem; printed on Aug. 27, 2005.
“Bayesian inference”; Wikipedia, the free encyclopedia; pp. 1-9; located at: http://en.wikipedia.org/wiki/Bayesian—inference#Evidence—and—the—scientific—method; printed on Aug. 27, 2005.
“Bayesian logic”; a Whatis.com definition; p. 1; located at: http://whatis.techtarget.com/definition/0,,sid9—gci548993,00.html; printed on Aug. 19, 2005.
“Bayesian probability”; Wikipedia, the free encyclopedia; pp. 1-4; located at: http://en.wikipedia.org/wiki/Bayesianism; printed on Aug. 27, 2005.
Calder, Brad; Grunwald, Dirk; Lindsay, Donald; Martin, James; Mozer, Michael; Zorn, Benjamin; “Corpus-based Static Branch Prediction”; pp. 1-14; located at: http://www.cse.ucsd.edu/˜calder/papers/PLDI-95-ESP.pdf.
Gomez, Faustino J.; Burger, Doug; Miikkulainen, Risto; “A Neuroevolution Method for Dynamic Resource Allocation on a Chip Multiprocessor”; bearing a date of 2001; pp. 1-6; printed on Aug. 25, 2005.
McFarling, Scott; “Combining Branch Predictors”; WRL Technical Note TN-36; Jun. 1993; pp. 1-29; located at: http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-36.pdf; printed on Aug.
Ferren Bran
Hillis W. Daniel
Myhrvold Nathan P.
Tegreene Clarence T.
Wood, Jr. Lowell L.
Chan Eddie P
Faherty Corey S
Searete LLC
LandOfFree
Optimization of a hardware resource shared by a multiprocessor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimization of a hardware resource shared by a multiprocessor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimization of a hardware resource shared by a multiprocessor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4106186