Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-10-23
2004-07-13
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S213000, C712S203000, C717S107000, C717S141000
Reexamination Certificate
active
06763449
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an operation-processing apparatus and, more particularly, to an operation-processing apparatus that is suitably used for executing a customized operation wherein an extension instruction (new instruction) is added to an existing instruction.
BACKGROUND OF THE INVENTION
Recently, owing to a demand for the enhancement in the performance of computers, the competition for the development of operation-processing apparatuses such as CPU (Central Processing Unit) or MPU (Micro Processing Unit) has become more and more vigorous. The existing circumstance therefore is that the developing makers have had to put operation-processing apparatuses each having a new function loaded therein into the markets one after another. Therefore, at how low a cost and in how short a period they can develop their operation-processing apparatus have been being a key for predomination over the markets.
An operation-processing apparatus is incorporated into every piece of computer from personal computers to super-computers. It is, in other words, an apparatus that is a main requisite for any computer. Generally, it is comprised of an instruction decoder for decoding an operation instruction, an operation-executing unit for executing various types of operation such as an arithmetic operation or logical operation according to an operation instruction (operation codes) obtained from the decoding performed by the instruction decoder, a register for temporarily storing the result of the operation (the operated-result data) executed by the operation-executing unit, and control circuits (e.g., a pipeline control circuit, a state machine, etc.) for executing the control of the operation-executing unit, for executing the control of the storage of the operated-result data into a register (e.g., an integer register or a floating-point numeric-value register), etc. In this operation-processing apparatus, various types of operation each according with a relevant instruction and the storage of the operated-result data are executed with an ultra-high speed.
By the way, as stated above, in the conventional operation-processing apparatus, the customizing wherein a new operation instruction (hereinafter referred to as “an extension instruction” is added to an existing operation instruction (hereinafter referred to as “an existing instruction”) is performed. In this customizing, in case that the contents of the operation corresponding to the existing instruction and those corresponding to the extension instruction differ from each other or in case that the extension instruction cannot be executed in an applied form wherein the existing instruction is used as an application therefor, a control circuit corresponding to the extension instruction must be additionally provided. For this reason, there was the problem that the portions where a change in design of the existing mechanism is made were increased in number.
Also, in the conventional operation-processing apparatus, integral operated-result data is stored in an integer register while floating-point operated-result data is registered in a floating-point numeric-value register. Namely, in general, the type of the operated-result data (integer or floating-point numeric value) and the type of the register are the same. Here, there is a case where, according to the demand of the customizing, a special extension instruction is added of that a different type of operated-result data is to be stored in the register. In this kind of customizing, an existing path for leading the operated-result data to the register must be re-designed. Therefore, there was the problem that the change in design had to be made on a large scale.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an operation-processing apparatus in which an extension instruction can be added to an existing mechanism with a minimum necessary change in design with respect thereto.
To attain the above object, according to the first aspect of the invention, there is provided an operation-processing apparatus comprising instruction-decoding means (corresponding to an instruction decoder
10
of a first embodiment as later described) for decoding an existing instruction and an extension instruction into the same operation code including at least instruction-type-determining information for determining the existing instruction or the extension instruction, existing-operation-executing means (corresponding to an existing-operation-executing unit
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A of the first embodiment as later described) for executing an existing operation according to the operation code and outputting an operation-termination-notifying signal, extension-operation-executing means (corresponding to an extension-operation-executing unit
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B of the first embodiment as later described) that operates in synchronism with the existing-operation-executing means to thereby execute an extension operation according to the operation code, instruction-type-determining means (corresponding to a control circuit
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of the first embodiment as later described) for determining the type of the instruction according to the instruction-type-determining information, and selecting means (corresponding to a multiplexer
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of the first embodiment as later described) for, when the type of the instruction has been determined to be the extension instruction and the operation-termination-notifying signal has been input, selecting operated-result data of the extension-operation-executing means.
According to the above-described invention, when the extension instruction is issued, the extension instruction is decoded into the operation code by the instruction-decoding means. This operation codes is notified to both of the existing-operation-executing means and the extension-operation means, which synchronously execute their relevant operations. And, upon completion of the operations, an operation-termination-notifying signal is output from the existing-operation-executing means. Assume here that it is being determined that the type of the instruction is the extension instruction. Then, the selecting means selects the operated-result data of the extension-operation-executing means.
In this way, according to the above-described invention, the operation code is made to contain the instruction-type-determining information. Thereby, even when the extension instruction has been issued, utilizing the operation-termination-notifying signal output from the existing-operation-executing means, the termination of the operation of the extension-operation-executing means is recognized to thereby select the operated-result data of the extension-operation-executing means. Therefore, it is possible to add the extension instruction to the existing mechanism with a minimum necessary change in design made with respect thereto.
Also, according to the second aspect of the invention, in the operation-processing apparatus as described in the first aspect of the invention, the selecting means selects, when the type of the instruction has been determined to be the extension instruction and the operation-termination-notifying signal has been input, the operated-result data of the extension-operation-executing means.
According to this above-described invention, it is arranged that when the type of the instruction has been determined to be the existing instruction there is selected the operated-result data of the existing-operation-executing means. Therefore, it is possible to add the extension instruction without making any change of the existing-operation-executing means.
Also, according to the third aspect of the invention, there is provided an operation-processing apparatus comprising instruction-decoding means (corresponding to an instruction decoder
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of a second embodiment as later described) for decoding an existing instruction and an extension instruction into the same operation code including at least type-determining information for determining the type of operated-result data regarding a forwarded destination, e
Sugano Fumitake
Takeshita Katsunori
Fujitsu Limited
Pan Daniel H.
Staas & Halsey , LLP
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