Optimized storage system and method for a processor that execute

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...

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G06F 930

Patent

active

061311561

ABSTRACT:
An optimized storage system is implemented in a processor that executes instructions out of order. The system minimizes storage requirements for dependency operands in the processor by eliminating a need for separate storage mechanisms for holding different dependency operands that are produced from different instructions. The system comprises the following elements. An instruction reordering mechanism is configured to permit execution of the instructions in an out of order sequence. Rename registers (RRs) are associated with the reordering mechanism. Logic causes storage of trap information in the rename registers intermixed with instruction execution results. The trap information may be associated with arithmetic integer or floating point (fp) operations and can include the identity of the trapped instruction, the trapped operation, etc. Logic further causes storage of different sized dependency operands within the RRs. The dependency operands can include, for example, carry borrow (cb) operands and/or shift amount register (sar) operands. The dependency operands are produced by instructions and stored in the rename registers and are also retrieved and utilized by instructions. Significantly, operand dependencies of different types and sizes can be stored and intermixed in the same set of rename registers.

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Val Popescu, "Ther Metaflow Architecture", IEEE Micro, pp. 10-13 and 64-73, 1991.

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