Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Patent
1996-03-26
1999-07-06
Maung, Zarni
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
711 3, 711100, 711123, 711141, 712207, 712237, G06F 1200, G06F 1300
Patent
active
059192569
ABSTRACT:
A structure for, and a method of operating, an operand cache to store operands retrieved from a memory. An instruction requiring an operand stored in the memory, is allowed to speculatively execute in an execution unit of a processor using an operand stored in an entry (corresponding to the address of the instruction) of the operand cache. When the actual operand is later retrieved from the memory it is compared to the cached operand used for speculative execution. If the cached and actual operands are unequal then the speculatively executed instruction and all subsequent instructions are aborted and the processor resumes execution at the address of the instruction that was speculatively executed.
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Sowadsky Elliot A.
Widigen Larry
Advanced Micro Devices , Inc.
Barot Bharat
Maung Zarni
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