Result data forwarding in parallel vector data processor...
Result forwarding cache
Result forwarding cache
Result forwarding of either input operand to same operand...
Result path sharing between a plurality of execution units...
Resuming normal execution by restoring without refetching instru
Resuming thread to service ready port transferring data...
Retaining flag value associated with dead result data in...
Retiring early-completion instructions to improve computer...
Retiring early-completion instructions to improve computer...
Retiring instructions that meet the early-retirement...
Return address predictor that uses branch instructions to...
Return address stack including speculative return address...
Return address stack recovery in a speculative execution...
Return register stack target predictor
Return target address prediction by moving entry pointer to...
Reuseable configuration data
Reusing a buffer memory as a microcache for program...
RISC CPU instructions particularly suited for decoding...
RISC microprocessor architecture implementing multiple typed reg