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Result data forwarding in parallel vector data processor...

Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
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Result forwarding cache

Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
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Result forwarding cache

Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
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Result forwarding of either input operand to same operand...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Result path sharing between a plurality of execution units...

Electrical computers and digital processing systems: processing – Instruction issuing
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Resuming normal execution by restoring without refetching instru

Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
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Resuming thread to service ready port transferring data...

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Retaining flag value associated with dead result data in...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Retiring early-completion instructions to improve computer...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Retiring early-completion instructions to improve computer...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Retiring instructions that meet the early-retirement...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Return address predictor that uses branch instructions to...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Return address stack including speculative return address...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Return address stack recovery in a speculative execution...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Return register stack target predictor

Electrical computers and digital processing systems: processing – Processing control – Branching
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Return target address prediction by moving entry pointer to...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Reuseable configuration data

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Reusing a buffer memory as a microcache for program...

Electrical computers and digital processing systems: processing – Processing control – Branching
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RISC CPU instructions particularly suited for decoding...

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
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RISC microprocessor architecture implementing multiple typed reg

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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