Result data forwarding in parallel vector data processor...

Electrical computers and digital processing systems: processing – Processing architecture – Vector processor

Reexamination Certificate

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C712S222000, C712S225000

Reexamination Certificate

active

07660967

ABSTRACT:
A computer processor is responsive to successive processing instructions in an issue order to process regular vectors to generate a result vector without use of a cache. At least two architectural registers having input-vector capability are selectively coupled to memory to receive corresponding vector-elements of two vectors and transfer the vector-elements to a selected functional unit. At least one architectural register having output capability is selectively coupled to an output, which in turn is coupled to transfer result vector-elements to the memory. The functional unit performs a function on the vector-elements to generate a respective result-element. The result-elements are transferred to a selected architectural register for processing as operands in performance of further functions by a functional unit, or are transferred to the output for transfer to memory. In either case, the order of the result vector-elements is restored to the issue order of the successive processing instructions.In some embodiments, restore order buffers operate with issue-order codes of result-elements in result registers and architectural registers to restore order to the result vector-elements for output to memory.

REFERENCES:
patent: 4760545 (1988-07-01), Inagami et al.
patent: 4837730 (1989-06-01), Cook et al.
K. Asanovic, “Appendix G, Vector Processors”, published on the Internet at http://books.elsevier.com/companions/1558605967/appendices/1558605967-appendix-g.pdf (2003).
Wikipedia Encyclopedia, “SIMD” (Single Instruction, Multiple Data), published on the internet at http://en.wikipedia.org/wiki/SIMD,(Oct. 6, 2007).

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