Result path sharing between a plurality of execution units...

Details Result path sharing between a plurality of execution units... Result path sharing between a plurality of execution units...

2009-06-01

2011-11-01

Faherty, Corey S. (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S215000, C712S218000

Reexamination Certificate

active

08051275

ABSTRACT:
A processor2includes an execution cluster10having multiple execution units14, 16, 18, 20. The execution units14, 16, 18, 20share result buses22, 24. Issue circuitry12within the execution cluster10determines future availability of a result bus22, 24for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register32storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.

REFERENCES:
patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6311261 (2001-10-01), Chamdani et al.
patent: 2009/0198974 (2009-08-01), Barowski et al.
Smith et al.; Implementation of Precise Interrupts in Pipelined Processors; 1985; IEEE.
Pleszkun et al.; The Performance of Multiple Functional Unit Processors; 1988; IEEE.
Shen et al; Modern Processor Design; Beta Edition; 2003; McGraw-Hill.

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