Return target address prediction by moving entry pointer to...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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C712S238000, C712S239000, C712S240000

Reexamination Certificate

active

07925870

ABSTRACT:
An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The entry designation unit computes a designate entry position in a return address stack by, changing the designate entry to indicate a one-step shallower entry when a call instruction is predicted during the instruction fetching, changing the designate entry independently of a push or pop operation to indicate a one-step deeper entry when a return instruction is predicted during an instruction fetching, and changing the designate entry depending upon a push and a pop operation when a call and return instruction is completed, thereby keeping a position of the designate entry. The entry designation unit designates an entry as predicted return address of a subroutine when the fetched instruction hitsin a branch history and determined as a return instruction.

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