Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2006-05-09
2006-05-09
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S216000, C712S218000
Reexamination Certificate
active
07043626
ABSTRACT:
A method and apparatus for retaining flag values when an associated data value dies. A first storage circuit includes a free list for storing physical register names (PRNs) and indications indicative of whether a physical register associated with a PRN was assigned to store a logical register result and flag results of a first instruction and a logical register result and a subsequent instruction which overwrites the logical register result but not the flags. A second storage circuit stores PRNs separate from the free list. The first and second storage circuits output first and second PRNs to a selection circuit. If the first indication (associated with the first PRN) is in a first state, the selection circuit may provide the first PRN to a mapper for assignment to a logical register. If the first indication is in a second state, the second PRN may be provided to the mapper.
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Val Popescu, et al., “The Metaflow Architecture”, IEEE Micro, Jun. 1991, 15 pages.
Alsup Mitchell
McMinn Brian D.
Pickett James K.
Advanced Micro Devices , Inc.
Heter Erik A.
Kim Kenneth S.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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