Resuming thread to service ready port transferring data...

Details Resuming thread to service ready port transferring data... Resuming thread to service ready port transferring data...

2007-04-17

2009-11-03

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C710S015000, C712S038000

Reexamination Certificate

active

07613909

ABSTRACT:
A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal.

REFERENCES:
patent: 5592488 (1997-01-01), Thomann et al.
patent: 6947425 (2005-09-01), Hooper et al.
patent: 7457246 (2008-11-01), Zhang
patent: 2006/0259669 (2006-11-01), Dockser et al.
patent: 2006058242 (2006-06-01), None
International Search Report and Written Opinion of the International Searching Authority dated Sep. 1, 2008.

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