Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2007-01-11
2009-08-04
Treat, William M (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
07571305
ABSTRACT:
A data processing system2includes an instruction cache6having an associated buffer memory18, 8. The buffer memory18, 8can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry20. When operating in the microcache mode, instruction data is read from the buffer memory18, 8without requiring an access to the instruction cache6.
REFERENCES:
patent: 2005/0015537 (2005-01-01), Asaad et al.
de Alba et al.,Path-based Hardware Loop Prediction, 10 pages.
Reinman et al.,Optimizations Enabled by a Decoupled Front-End Architecture, 32 pages.
Brochier Stephane Eric Sabastien
Grandou Gilles Eric
Mouton Louis-Marie Vincent
Piry Fredrick Claude Marie
ARM Limited
Nixon & Vanderhye P.C.
Treat William M
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