RISC microprocessor architecture implementing multiple typed reg

Details RISC microprocessor architecture implementing multiple typed reg RISC microprocessor architecture implementing multiple typed reg

1998-11-10

2000-03-28

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712278, G06F 1500

Patent

active

060444495

ABSTRACT:
A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

REFERENCES:
patent: 4212076 (1980-07-01), Conners
patent: 4626989 (1986-12-01), Torii
patent: 4675806 (1987-06-01), Uchida
patent: 4722049 (1988-01-01), Lahti
patent: 4807115 (1989-02-01), Torng
patent: 5125092 (1992-06-01), Prener
patent: 5201056 (1993-04-01), Daniel et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5241636 (1993-08-01), Kohn
patent: 5442757 (1995-08-01), McFarland et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5493687 (1996-02-01), Garg et al.
patent: 5560035 (1996-09-01), Garg et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5592636 (1997-01-01), Popescu et al.
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5627983 (1997-05-01), Popescu et al.
patent: 5682546 (1997-10-01), Garg et al.
patent: 5708841 (1998-01-01), Popescu et al.
patent: 5768575 (1998-06-01), McFarland et al.
patent: 5797025 (1998-08-01), Popescu et al.
patent: 5832293 (1998-11-01), Popescu et al.
patent: 5838586 (1998-11-01), Garg et al.
patent: 5838986 (1998-11-01), Garg et al.
Adams et al. Utilising Low Level Parallelism in General Purpose Code: Harp Project pp. 12-24, Oct. 1990.
Smith et al., "Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Sympsium on Computer Architecture, Jun. 1985, pp. 36-44.
Wedig, R.G., Detection of Concurrency In Directly Executed Language Instrtuction Streams, (Dissertation), Jun. 1982, pp. 1-179.
Agerwala et al., "High Performance Reduced Instruction Set Processors," IBM Research Division, Mar. 31, 1987, pp. 1-61.
Gross et al., "Optimizing Delayed Branches," Proceedings of the 5th Annual Workshop on Microprogramming, Oct. 5-7, 1982, pp. 114-120.
Tjaden et al., "Representation of Concurrency with Ordering Matrices," IEEE Trans. On Computers, vol. C-22, No. 8, Aug. 1973, pp. 752-761.
Tjaden, Representation and Detection of Concurrency Using Ordering Matrices, (Dissertation), 1972, pp. 1-199.
Foster et al., "Percolation of Code to Enhance Parallel Dispatching and Execution," IEEE Trans. On Computers, Dec. 1971, pp. 1411-1415.
Thornton, J.E., Design of a Computer: The Control Data 6600, Control Data Corporation, 1970, pp. 58-140.
Weiss et al., "Instruction Issue Logic in Pipelined Supercomputers," Reprinted from IEEE Trans. on Computers, vol. C-33, No. 11, Nov. 1984, pp. 1013-1022.
Tomasulo, R.M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, vol. 11, Jan. 1967, pp. 25-33.
Tjaden et al., "Detection and Parallel Execution of Independent Instructions," IEEE Trans. On Computers, vol. C-19, No. 10, Oct. 1970, pp. 889-895.
Smith et al., "Limits on Multiple Instruction Issue," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 290-302.
Pleszkun et al., "The Performance Potential of Multiple Functional Unit Processors," Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, pp. 37-44.
Pleszkun et al., "WISQ: A Restartable Architecture Using Queues," Proceedings of the 14th International Symposium on Computer Architecture, Jun. 1987, pp. 290-299.
Patt et al., "Critical Issues Regarding HPS, A High Performance Microarchitecture," Proceedings of the 18th Annual Workshop on Microprogramming, Dec. 1985, pp. 109-116.
Hwu et al., "Checkpoint Repair for High-Performance Out-of-Order Execution Machines," IEEE Trans. On Computers, vol. C-36, No. 12, Dec. 1987, pp. 1496-1514.
Patt et al., "HPS, A New Microarchitecture: Rationale and Introduction," Proceedings of the 18th Annual Workshop on Microprogramming, Dec. 1985, pp. 103-108.
Keller, R.M., "Look-Ahead Processors," Computing Surveys, vol. 7, No. 4, Dec. 1975, pp. 177-195.
Jouppi et al., "Avaialable Instruction-Level Parallelism for Superscalar and Superpipelined Machines," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 272-282.
Hwu et al., "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality," Proceedings from ISCA-13, Tokyo, Japan, Jun. 2-5, 1986, pp. 297-306.
Hwu et al., "Exploiting Parallel Microprocessor Microarchitectures with a Compiler Code Generator," Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, pp. 45-53.
Colwell et al., "A VLIW Architecture for a Trace Scheduling Compiler," Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1987, pp. 180-192.
Uht, A.K., "An Efficient Hardware Algorithm to Extract Concurrency From General-Purpose Code," Proceedings of the 19th Annual Hawaii International Conference on System Sciences, 1986, pp. 41-50.
Charlesworth, A.E., "An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family," Computer, vol. 14, Sep. 1981, pp. 18-27.
Acosta, Ramon D. et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions On Computers, vol. C-35, No. 9, Sep. 1986, pp. 815-828.
Johnson, William M., Super-Scalar Processor Design, (Dissertation), Copyright 1989, 134 pages.
Sohi, Gurindar S. and Sriram Vajapeyam, "Instruction Issue Logic For High-Performance, Interruptable Pipelined Processors," Conference Proceedings of the 14.sup.th Annual International Symposium on Computer Architecture, Jun. 2-5, 1987, pp. 27-34.
Smith, M.D. et al., "Boosting Beyond Static Scheduling in a Superscalar Processor," IEEE, 1990, pp. 344-354.
Murakami, K. et al., "SIMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture," ACM, 1989, pp. 78-85.
Jouppi, N.P., "The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," IEEE Transactions on Computers, vol. 38, No. 12, Dec. 1989, pp. 1645-1658.
Horst, R.W. et al., "Multiple Instruction Issue in the NonStop Cyclone Processor," IEEE, 1990, pp. 216-226.
Goodman, J.R. and Hsu, W., "Code Scheduling and Register Allocation in Large Basic Blocks," ACM, 1988, pp. 442-452.
Lam, M.S., "Instruction Scheduling For Superscalar Architectures," Annu. Rev. Comput. Sci., vol. 4, 1990, pp. 173-201.
Aiken, A. and Nicolau, A., "Perfect Pipelining: A New Loop Parallelization Technique*," pp. 221-235.
Jouppi, N.H., "Integration and Packaging Plateaus of Processor Performance," IEEE, 1989, pp. 229-232.
Patterson et al., "A VLSI RISC," IEEE Computer, vol. 15, No. 9, pp. 8-18, Sep. 1982.
Maejima et al., "A 16-bit Microprocessor with Multi-Register Bank Architecture," Proc. Fall Join

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