Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-03-31
2001-10-23
Pan, Daniel H. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S036000, C712S035000, C712S037000, C712S224000, C712S223000, C709S247000, C709S241000, C707S793000
Reexamination Certificate
active
06308253
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to integrated circuit device architecture, and more particularly, to an integrated circuit device architecture for use in digital signal processing applications.
BACKGROUND OF THE INVENTION
Future generations of audio/video processing circuitry will continue to have to break new ground in performance to satisfy consumers' desires for greater functionality and higher audio/video quality in consumer electronic devices such as computers, televisions, direct broadcast satellite (DBS) receivers, audio/video (A/V) receivers, digital versatile disc (DVD) players, cable set-top boxes, etc. (referred to hereinafter as A/V components). In particular, emerging standards such as the Advanced Television Systems Committee (ATSC) digital television specification, the MPEG-2 video decoding specification, the Dolby AC3 audio decoding specification, etc., have significantly raised the performance requirements for the hardware circuitry used in such devices.
Decoding is a process of retrieving information from a data stream and formatting the data in a useable form. Decoding is a form of digital signal processing (DSP), and is typically handled by dedicated DSP circuitry in an integrated circuit device, or “chip.” A number of other DSP functions or operations may be used in A/V components, e.g., filtering, demultiplexing, close captioning decoding, graphics overlaying, etc.
At one time, separate DSP chips were used in a given design to implement the various digital signal processing tasks, or operations, required in an A/V component. The DSP chips were mounted on a circuit board with a main programmable controller such as a microprocessor, with electrical connections provided between the various chips to permit data to be transmitted therebetween.
However, as the performance requirements of such components have grown, and as chip manufacturing techniques have improved, a significant need has developed for a manner of integrating the functionality of multiple DSP chips onto the same integrated circuit device. The benefits of integrating multiple functions onto the same chip often include greater performance, lower design and manufacturing costs, reduced component size, and reduced power requirements, among others.
Two primary integration approaches are often used to implement multiple DSP functions on a given integrated circuit device. A first approach is a completely hardwired approach, where dedicated circuitry, typically in the format of one or more hardwired datapaths, is developed to implement each DSP function. Additional dedicated circuitry is then developed to transmit data between the various DSP functions. Typically, a hardwired approach offers the greatest performance, since circuitry may be optimized for one particular application. As a result, hardwired circuitry often minimizes memory requirements and circuit area, and maximizes circuit speed, for its given application.
The primary drawback to the hardwired approach, however, is the lack of flexibility resulting from the optimization for one particular application. A hardwired chip is typically designed and manufactured to work in one environment and to perform one specific set of functions. Upgrading or extending the functionality of a hardwired chip design often requires a complete redesign. Given that most of the cost in a chip is invested in its design, therefore, the hardwired approach can be relatively costly. Moreover, the hardwired approach typically has a relatively long development time, which can adversely affect a manufacturer's ability to respond quickly to consumer needs.
At the other end of the spectrum from the hardwired approach is the completely programmable (or software-based) approach, which, similar to a general purpose computer, attempts to support multiple applications by providing a relatively generic hardware platform that can be customized via software for use in different applications. Many software-based DSP architectures use very long instruction word (VLIW) processors, which provide extremely flexible and reconfigurable functionality for a wide variety of applications. Under this approach, the same integrated circuit device can be used to perform any number of functions merely by executing different software supplied to the device. Moreover, given that software is relatively easier and faster to design and troubleshoot than hardware, development is relatively faster and less expensive.
However, a purely software-based approach suffers from a number of drawbacks. First, using generic hardware typically requires compromises to be made to support multiple applications. As a result, many of the optimizations that might be made in a completely hardwired approach cannot be made for a software-based design. Consequently, the overall performance of a software-based design is often less optimal than a completely hardwired design.
Second, software-based designs typically require a very sophisticated compiler, a program used to convert human-readable program code into machine-readable instructions. Overall development costs and time thus increase due to the additional up-front effort and expense associated with developing the compiler.
Third, software-based designs also require a relatively sophisticated real time operating system that supports complicated scheduling of different tasks and threads. As a result, additional development efforts must be expended in this area as well, again increasing development costs and time. Furthermore, a complex multi-tasking operating system often introduces significant additional overhead, thereby further limiting performance and increasing memory requirements.
Therefore, a significant need exists for a manner of integrating DSP circuitry into an integrated circuit device to provide a better balance of development time, development expense, performance, flexibility, and upgradability.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing a circuit arrangement and method that utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes a very small CPU, known as a programmable controller, which is a reduced instruction set (RISC) processor supporting a small number of useful instructions for digital signal processing.
Specifically, one aspect of the invention is a pair of instructions supported by the programmable controller, known as extract and insert, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register.
The extract instruction identifies a source register, a target register, a number of bits and a starting position; in response to this instruction the identified number of bits, starting from the identified starting position, are copied from the source register to a predetermined position in the target register, e.g., a right justified position. In the specific embodiment disclosed herein, the remaining bits of the target register are cleared.
The insert instruction identifies a source register, a target register, a number of bits and a starting position; in response to this instruction the identified number of bits are copied from a predetermined position in the source register, e.g., a right justified position, to the target register, starting at the identified starting position.
A second aspect of the invention is a pair of leading value detect instructions supported by the programmable controller, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.
The leading value detect instruction i
Gadre Shirish
Khurshid Mazin S.
Pan Daniel H.
Sony Corporation
Wood Herron & Evans L.L.P.
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