Multimedia-instruction acceleration device for increasing...
Multiple channel data bus routing switching including parity gen
Multiple control sequences per row of microcode ROM
Multiple coprocessor architecture to process a plurality of...
Multiple data hazards detection and resolution unit
Multiple entry points for system call instructions
Multiple execution of instruction loops within a processor...
Multiple global pattern history tables for branch prediction in
Multiple instruction execution mode resource-constrained device
Multiple instruction set decoding
Multiple ISA support by a processor using primitive operations
Multiple issue static speculative instruction scheduling with pa
Multiple logical interfaces to a shared coprocessor resource
Multiple machine view execution in a computer system
Multiple native instruction set master/slave processor arrangeme
Multiple processor apparatus having a protocol processor intende
Multiple processor arrangement for conserving power
Multiple processor cellular radio
Multiple processor, distributed memory computer with out-of-orde
Multiple processor, distributed memory computer with out-of-orde