Multiple instruction set decoding

Details Multiple instruction set decoding Multiple instruction set decoding

2011-06-07

2011-06-07

Petranek, Jacob (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C712S212000

Reexamination Certificate

active

07958335

ABSTRACT:
A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit. Accordingly, this can significantly reduce the amount of logic duplicated in the decoder units which, in turn, reduces the amount chip area required to support decoding and reduces power consumption. Also, since the decode units are no longer required to support the decoding of such a high number of different instructions, the complexity of each decode unit can be reduced, which can result in increased performance during decode.

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Hennessy, John, Patterson, David. “Computer Architecture: A Quantitative Approach” Morgan Kaufmann, pp. 1-1141, May 17, 2002.

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