Multiple processor, distributed memory computer with out-of-orde

Details Multiple processor, distributed memory computer with out-of-orde Multiple processor, distributed memory computer with out-of-orde

1999-04-21

2000-05-09

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

712 3, 712 11, G06F 1500

Patent

active

060617764

ABSTRACT:
A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

REFERENCES:
patent: 5887138 (1999-03-01), Hagersten et al.
Burger et al., Memory Bandwidth Limitation of Future Microprocessors; May 1996.
Kagi et al., An Analysis of the Interactions of Overhead-Reducing Techniques for Shared-Memory Multiprocessors, Jul. 1996.
Kaxiras, Kiloprocessor Extensions to SCI 1996.
Burger et al., The Declining Effectiveness of Dynamic Caching for General-Purpose Microprocessor Jan. 1995.
Kaxiras et al., The GLOW Cache Coherence Protocol Extensions for Widely Shared Data, May 1996.
Burger et al., DataScalar Architectures Jun. 1997.

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