Multiple global pattern history tables for branch prediction in

Electrical computers and digital processing systems: processing – Processing control – Branching

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712239, 712238, G06F 932

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active

059352418

ABSTRACT:
A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction. A range register unit (75) for determining whether the instruction is contained within an address range is also disclosed as used in the selection of the pattern history table (53).

REFERENCES:
patent: 5574871 (1996-11-01), Hoyt et al.
patent: 5577217 (1996-11-01), Hoyt et al.
"The Predictability of Branches is Libraries," Brad Calder, Dirk Grunwald, and Amitabh Srivastava, WRL Research Report 95/6, Oct. 1995.
"A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History," Tse-Yu Yeh and Yale N. Patt, 1993.
"Alternative Implementations of Two-Level Adaptive Branch Prediction," Tse-Yu Yen and Yale N. Patt, 1992.
Pentium Pro Family Developer's Manual, vol. 3: Operating System Writers's Guide, 1996.
"Two-Level Adaptive Training Branch Prediction," Tse-Yu Yeh and Yale N. Patt, 1991.

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