Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1994-06-09
2000-02-08
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
712 32, 710 2, 710 3, 714 6, G06F 1312
Patent
active
060237546
ABSTRACT:
A bus switch providing versatile data path routing between a first group of busses associated with a disk array controller and a second group of busses associated with the individual disk drives within the disk array. The bus switch comprises a plurality of bus multiplexers, equal in number to the number of drive busses. Each bus multiplexer includes a plurality of inputs, each input being connected to a corresponding one of the controller busses. The multiplexers are responsive to select and enable signals to connect selected controller busses to selected drive busses. The bus switch additionally includes a plurality of bus multiplexers for directing data from the drive busses to the controller busses. A parity generator comprising an exclusive-OR circuit is integrated with the bus switch. The output of the parity generator is also provided to each of the multiplexers and can be directed thereby to any of the controller or drive busses.
REFERENCES:
patent: 3648255 (1972-03-01), Beausoleil et al.
patent: 3916380 (1975-10-01), Fletcher et al.
patent: 4024498 (1977-05-01), McIntosh
patent: 4386416 (1983-05-01), Giltner et al.
patent: 4404650 (1983-09-01), Kleinert
patent: 4446515 (1984-05-01), Sauer et al.
patent: 4494196 (1985-01-01), Greer
patent: 4503535 (1985-03-01), Budde et al.
patent: 4583194 (1986-04-01), Cage
patent: 4600990 (1986-07-01), Gershenson et al.
patent: 4612613 (1986-09-01), Gershenson et al.
patent: 4761785 (1988-08-01), Clark et al.
patent: 4773004 (1988-09-01), Gershenson et al.
patent: 4775978 (1988-10-01), Hartness
patent: 4821170 (1989-04-01), Bernick et al.
patent: 4914656 (1990-04-01), Dunphy, Jr. et al.
patent: 5140592 (1992-08-01), Idleman et al.
patent: 5175865 (1992-12-01), Hillis
patent: 5185876 (1993-02-01), Nguyen et al.
patent: 5206943 (1993-04-01), Callision et al.
patent: 5210860 (1993-05-01), Pfeffer et al.
"A Case for Redundant Arrays of Inexpensive Disks (RAID)" by David A. Patterson, et al., Computer Science Division (EECS), University of California, Report No. UCB/CSD 87/391; Dec. 1987.
"Parity Striping of Disc Arrays: Low-Cost Reliable Storage With Acceptable Throughput" by Jim Gray, et al., Tandem Computers, Technical Report 90.2, Jan. 1990, Part No.: 39596.
Courtright, II William V.
DuLac Keith B.
An Meng-Ai T.
Hyundai Electronics America
Nguyen Dzung C.
LandOfFree
Multiple channel data bus routing switching including parity gen does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple channel data bus routing switching including parity gen, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple channel data bus routing switching including parity gen will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1689049