Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2006-06-16
2011-10-18
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C718S108000
Reexamination Certificate
active
08041929
ABSTRACT:
Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2cregisters for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2Tthreads. A particular register is accessed in a register bank that has 2(C+T)registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.
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Gamer Trevor
Goss Gegory
Jeter Robert
Lee William
Smith Scott
Cisco Technology Inc.
Pan Daniel
Patent Capital Group
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