Target instructions prefetch cache

Details Target instructions prefetch cache Target instructions prefetch cache

1997-03-28

1999-11-16

Maung, Zarni

Electrical computers and digital processing systems: processing

Processing control

Branching

G06F 938

Patent

active

059875992

ABSTRACT:
A processor that includes an execution pipeline that executes a programmed flow of instructions is provided. The processor also includes an instruction pointer generator configured to generate an instruction pointer. Furthermore, the processor includes a branch prediction circuit configured to receive the instruction pointer. In response to the instruction pointer, the branch prediction circuit is configured to determine if an instruction corresponding to the instruction pointer includes a branch that is predicted taken and if so to provide to said execution pipeline a target instruction corresponding to said instruction. The branch prediction circuit provides to the execution pipeline at least one target instruction corresponding to the instruction corresponding to the instruction pointer.

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Perleburg, Chris H. et al.; "Branch Target Buffer Design and Optimization"; IEEE Transactions on Computers; pp. 396-412, Apr. 1993.

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