Identification bit at a predetermined instruction location...
Identifying execution ready instructions and allocating...
Information processing system and information processing method
Information processor
Inhibiting of a co-issuing instruction in a processor having...
Instruction alignment unit employing dual instruction queues for
Instruction buffer and method of controlling the instruction...
Instruction cache association crossbar switch
Instruction cache associative crossbar switch
Instruction control device and method therefor
Instruction decoder/dispatch
Instruction grouping history on fetch-side dispatch group...
Instruction queue evaluating dependency vector in portions...
Instruction vector-mode processing in multi-lane processor...
Instruction/skid buffers in a multithreading microprocessor...
Integration of multi-stage execution units with a scheduler for
Interfacing external thread prioritizing policy enforcing...
Issuing load-dependent instructions in an issue queue in a...