Parallel processing unit and instruction issuing system

Partitioned issue queue and allocation strategy

Passing decoded instructions to both trace cache building...

Pipe scheduling for pipelines based on destination register...

Pipeline control for high-frequency pipelined designs

Pipelined instruction dispatch unit in a superscalar processor

Pipelined instruction dispatch unit in a superscalar processor

Placing front instruction in replay loop to front to place...

Power optimized replay of blocked operations in a pipilined...

Pre-steering register renamed instructions to execution unit...

Predecoding and steering mechanism for instructions in a supersc

Prediction based instruction steering to wide or narrow...

Preferential dispatching of computer program instructions

Preventing the execution of a set of instructions in...

Prioritized issuing of operation dedicated execution unit...

Prioritizing thread selection partly based on stall...

Processing pipeline having stage-specific thread selection...

Processing unit incorporating multirate execution unit

Processor

Processor