Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2005-02-04
2010-12-14
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Reexamination Certificate
active
07853777
ABSTRACT:
An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicator for indicating which of the fetched instructions in the buffer have already been dispatched for execution. An input for each thread indicates that one or more of the already-dispatched instructions in the buffer has been flushed from execution. Control logic for each thread updates the indicator to indicate the flushed instructions are no longer already-dispatched, in response to the input. This enables the processor to re-dispatch the flushed instructions from the buffer to avoid re-fetching the flushed instructions. In one embodiment, there are fewer buffers than threads, and they are dynamically allocatable by the threads. In one embodiment, a single integrated buffer is shared by all the threads.
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Jones Darren M.
Kinter Ryan C.
Uhler G. Michael
Vishin Sanjay
Chan Eddie P
MIPS Technologies Inc.
Sterne Kessler Goldstein & Fox P.L.L.C.
Vicary Keith
LandOfFree
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