Instruction alignment unit employing dual instruction queues for

Details Instruction alignment unit employing dual instruction queues for Instruction alignment unit employing dual instruction queues for

1998-10-27

1999-09-14

Treat, William M.

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

712 23, G06F 938

Patent

active

059516755

ABSTRACT:
A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc., in determining which instructions to dispatch.

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