Instruction vector-mode processing in multi-lane processor...

Details Instruction vector-mode processing in multi-lane processor... Instruction vector-mode processing in multi-lane processor...

2006-11-15

2009-02-17

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S016000

Reexamination Certificate

active

07493475

ABSTRACT:
An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

REFERENCES:
patent: 5537606 (1996-07-01), Byrne
patent: 6272616 (2001-08-01), Fernando et al.
patent: 2005/0125640 (2005-06-01), Ford et al.
patent: 2005/0216700 (2005-09-01), Honary et al.
patent: 2006/0248320 (2006-11-01), Chin et al.
patent: WO99/31601 (1999-06-01), None
patent: WO03/096184 (2003-11-01), None
patent: WO2006/058358 (2006-06-01), None
Jouppi et al., “A Unified Vector/Scalar Floating-Point Architecture,” Digital, Western Research Laboratory, Research Report 89/8, Jul. 1989, pp. i-v, 1-23.
European Search Report from corresponding EP Application No. 07254379.6.

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