Making available instructions in double slot FIFO queue...

Management of both renamed and architected registers in a supers

Marking in history table instructions slowable/delayable for...

Measured, allocation of speculative branch instructions to...

Mechanism for eliminating the restart penalty when reissuing...

Mechanism for self-initiated instruction issuing and method...

Method and apparatus for accessing registers during deferred...

Method and apparatus for back to back issue of dependent...

Method and apparatus for back to back issue of dependent...

Method and apparatus for constructing a pre-scheduled...

Method and apparatus for controlling an instruction pipeline in

Method and apparatus for controlling an instruction pipeline...

Method and apparatus for determining availability of a queue...

Method and apparatus for determining availability of a queue...

Method and apparatus for dispatching instructions to execution u

Method and apparatus for distributing commands to a...

Method and apparatus for dual issue of program instructions to s

Method and apparatus for dual issue of program instructions...

Method and apparatus for executing instructions

Method and apparatus for forming and dispatching instruction...