Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
1999-12-16
2004-10-19
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
Reexamination Certificate
active
06807624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an instruction control device and a method therefor and, more particularly, to an instruction control device and a method for enabling an out-of-order instruction execution so as to execute instruction processing at high speed in an information processor.
2. Description of the Related Art
“Out-of-order instruction execution processing” means processing wherein those executable instructions, the inputted data for which have been completely collected, are occasionally executed in an order or sequence different from that instructed by a program. It is noted that the executions of instructions are performed in an arbitrary order in themselves, but instructions are executed such that resources, such as memory areas and register contents accessible from the program, are referred to and updated in the order instructed by the program so as to guarantee the processing results.
In an information processor in which an out-of-order instruction execution is permitted so as to execute an instruction processing at high speed, decoded instructions are once stored into decoded instruction storing means called a reservation station after the respective instruction decoding cycles. Next, irrespectively of a decoding order of the stored instructions, the decoded instruction, a source operand of which has been enabled, is selected and then the reservation station issues the instruction to an operator (such as computer, calculator).
However, in such a conventional instruction control device, there have been problems, as follows:
(1) In the conventional device, it has been necessary to distribute an instruction decoded information from an instruction register and an instruction decoded completion signal from a controlling unit, toward all entries within the reservation station. As a result, there were problems in that the sizes of logical circuits and intra-chip wiring areas are increased. There has been therefore caused problems that action delays are prolonged and more cycles are required.
Further, in the conventional device, there have been provided instruction order identifiers for respective entries so as to determine an instruction decoding order, and these identifiers must be compared with one another by means of a hardware comparator. As a result, there were also problems in that the aforementioned sizes and number of cycles are increased.
(2) If there exists an address dependency between instructions which request memory accesses, it should be guaranteed that the memory is referred to in a programmed order. However, if an address calculation and a request are performed in an out-of-order manner, there has been conventionally caused such a situation that, particularly when data are fetched by a succeeding instruction (such as LOAD instruction) from a memory area which has been updated by a preceding instruction (such as STORE instruction), the address of the preceding instruction is obtained after the fetch request of the succeeding instruction has been completed. Thus, it has been required to once cancel the succeeding instruction, and to newly refetch the succeeding instruction and decode the same again for re-execution thereof, thereby causing a problem that the execution speed of the memory operation instruction is considerably lowered.
(3) In the conventional device, in case that a preceding instruction executes an instruction such as a floating-point multiplication having longer operation cycles, there has been performed such processing that the starting of calculations of succeeding instructions are collectively held or stopped, and thereby the calculation result of the preceding instruction having longer operation cycles is forwarded to the succeeding instructions at predetermined later timings, respectively. Inherently, instructions should be executed independently from one another when no register interferences exist in an information processing that allows an out-of-order instruction execution, except that there exists register interference between instructions. Further, in such information processing, such as multiplier and adder processes within a CPU, should be capable of being parallelly operated, respectively, since they are provided as hardware different from each other. However, there has been a problem in conventional pipeline processing that instruction issuances are equally delayed after a multiply instruction processing as described above. This considerably reduces an operation efficiency such as of a product sum operation in which multiplication and addition are frequently repeated, as in a scientific calculation.
(4) In order to efficiently perform an out-of-order instruction execution at high speed, there is used a register renaming technique which guarantees that the register contents are referred to and updated in the programmed order. The register renaming technique is adapted to rename a logical register to allocate the logical register to physical registers or memories different from each other, to thereby allow a parallel execution of processings from a plurality of instructions when such processings can be executed independently from each other, even if the same register is competely used by the plurality of instructions. This is very effective mechanism for operating simple instructions at high speed.
According to such a technique, there can be performed an inter-register-register instruction, by forwarding processing, at high speed. However, concerning an inter-register-memory instruction, so as to guarantee that memory contents are referred to and updated in the programmed order, fetch access to the memory is conventionally delayed until data are stored into a cache memory. This results in reduction in operation performance.
SUMMARY OF THE INVENTION
In view of the conventional problems as described above, it is therefore an object of the present invention to provide an instruction control device and a method therefor which restricts the number of entries within a reservation station for storing decoded instructions upon issuance of the decoded instructions from an instruction register toward the reservation station, to thereby reduce the amount of hardware and cycle times. Further, it is also an object of the present invention to provide an instruction control device and a method therefor which deletes/compresses those entries issued to an execution unit so as to keep an instruction decoded order within the reservation station, to thereby eliminate the necessity of hardware for performing comparison processing relating to instruction order identifiers.
To this end, according to the present invention, there is provided an instruction control device and a method therefor, having instruction storing means for temporarily storing a plurality of decoded instructions as yet unissued to an execution unit; wherein the storing means is constituted such that an arranged order of entries of the storing means indicates a decoded order of decoded instructions stored in the entries; wherein that entry, from which the decoded instruction stored therein has been issued, is deleted; wherein information stored in the entries is shifted among the entries such that the entries storing the unissued instructions constitute entries in a continuous order; and wherein a shifting amount between entries is at the most equal to the number of instructions which can be simultaneously decoded.
In view of the above problem (2), it is a further object of the present invention to provide an instruction control device and a method therefor which controls an address calculation start time point of an instruction issued by the reservation station-by making use of simple decoding means, so as to prevent an address calculation request of a succeeding instruction from getting ahead of or surpassing that of a preceding instruction, to thereby allow a high speed calculation execution of a LOAD instruction succeeding to a STORE instruction.
To this end, according to the present invention, there is provided an ins
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