Electrical computers and digital processing systems: processing – Instruction issuing
Patent
1999-05-07
2000-12-12
Eng, David Y.
Electrical computers and digital processing systems: processing
Instruction issuing
G06F 924
Patent
active
061611735
ABSTRACT:
A superscalar processor includes a central scheduler for multiple execution units. The scheduler presumes operations issued to a particular execution unit all have the same latency, e.g., one clock cycle, even though some of the operations have longer latencies, e.g., two clock cycles. The execution unit that executes the operations having with longer than expected latencies, includes scheduling circuitry that holds up particular operation pipelines when operands required for the pipelines will not be valid when the scheduler presumes. Accordingly, the design of the scheduler can be simplified and can accommodate longer latency operations without being significantly redesigned for the longer latency operations.
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Ben-Meir Amos
Favor John G.
Krishna Ravi
Advanced Micro Devices , Inc.
Eng David Y.
Millers David T.
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