Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Patent
1997-07-07
1999-07-13
Ray, Gopal C.
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
712212, G06F 938
Patent
active
059220686
ABSTRACT:
An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
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Inoue Kiyoshi
Kamada Eiki
Kuriyama Kazunori
Shintani Yooichi
Shonai Tohru
Hitachi , Ltd.
Ray Gopal C.
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