Instruction buffer and method of controlling the instruction...

Details Instruction buffer and method of controlling the instruction... Instruction buffer and method of controlling the instruction...

2007-08-14

2007-08-14

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S216000, C712S217000

Reexamination Certificate

active

09862471

ABSTRACT:
An instruction buffer of the present invention includes a sequence of instructions arranged in an order determined beforehand, and a buffer including entries arranged in a preselected order for storing the sequence of instructions. Any one of the instructions stored in any one of the entries designated by a low entry number is prior, in order, to another instruction stored in another entry designated by a high entry number.

REFERENCES:
patent: 5740391 (1998-04-01), Hunt
patent: 5903918 (1999-05-01), Bauman et al.
patent: 6157998 (2000-12-01), Rupley et al.
patent: 6625746 (2003-09-01), Moore
patent: 60-173634 (1985-09-01), None
patent: 4-313121 (1992-11-01), None
patent: 5-204639 (1993-08-01), None
patent: 2000-181707 (2000-06-01), None
Hennessy et al. Computer Architecture: A Quantitative Approach, 3rdEdition, 2003, Morgan Kaufmann, San Francisco, pp. 182-184.
Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, 1991, pp. 44-49.
Japanese office action dated Nov. 20, 2003 with English translation of pertinent portions.

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