Identification bit at a predetermined instruction location...

Details Identification bit at a predetermined instruction location... Identification bit at a predetermined instruction location...

2007-06-19

2007-06-19

Fleming, Fritz (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S024000

Reexamination Certificate

active

09395294

ABSTRACT:
An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a single operation or two independent operations. The instruction includes designated bits at predetermined bit locations which identify whether the instruction is a long instruction or a dual operation instruction.

REFERENCES:
patent: 5051885 (1991-09-01), Yates et al.
patent: 5355460 (1994-10-01), Eickemeyer et al.
patent: 5761470 (1998-06-01), Yoshida
patent: 5870619 (1999-02-01), Wilkinson et al.
patent: 5878241 (1999-03-01), Wilkinson et al.
patent: 5966528 (1999-10-01), Wilkinson et al.
patent: 6076154 (2000-06-01), Van Eijndhoven et al.
patent: 6230180 (2001-05-01), Mohamed
patent: 6292845 (2001-09-01), Fleck et al.
patent: 6317820 (2001-11-01), Shiell et al.
patent: 6697774 (2004-02-01), Panesar
patent: 2000215061 (2000-08-01), None
patent: 2001142692 (2001-05-01), None

Affiliated with

Also associated with

Rating

Identification bit at a predetermined instruction location... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Identification bit at a predetermined instruction location..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Identification bit at a predetermined instruction location... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3860311