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Recorder buffer and a method for allocating a fixed amount of st

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Patent

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Reducing instruction transactions in a microprocessor

Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate

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Register access scheduling method for multi-bank register...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate

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Reissue logic for individually reissuing instructions trapped in

Electrical computers and digital processing systems: processing – Instruction issuing
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Reorder buffer configured to allocate storage for...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate

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Reorder buffer employed in a microprocessor to store instruction

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Rerouting VLIW instructions to accommodate execution units...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Result path sharing between a plurality of execution units...

Electrical computers and digital processing systems: processing – Instruction issuing
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