Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2005-02-04
2009-11-03
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction issuing
C718S103000
Reexamination Certificate
active
07613904
ABSTRACT:
A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.
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Jones Darren M.
Kinter Ryan C.
Kissell Kevin D.
Petersen Thomas A.
Kim Kenneth S
MIPS Technologies Inc.
Sterne Kessler Goldstein & Fox P.L.L.C.
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