Scheduler capable of issuing and reissuing dependency chains

Scheduler for use in a microprocessor that supports...

Scheduler which discovers non-speculative nature of an...

Scheduling operations using a dependency matrix

Select-free dynamic instruction scheduling

Self-checking code for tamper-resistance based on code...

Simultaneous multi-thread instructions issue to execution...

Speculative instruction issue in a simultaneously...

Speculative instruction issue in a simultaneously...

Speculative scheduling of instructions with source operand...

Stall optimization for an in-order, multi-stage processor...

Superscalar microprocessor having multi-pipe dispatch and...

Supplying halt signal to data processing unit from integer...

Supplying halt signal to data processing unit from integer...

Symmetrical instructions queue for high clock frequency scheduli

Synchronization primitives for flexible scheduling of...

Synchronization primitives for flexible scheduling of...

System and method for determining the relative age of...

System and method for high frequency stall design

System and method for improved branch performance in...