Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2007-09-11
2007-09-11
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S214000
Reexamination Certificate
active
10066984
ABSTRACT:
A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.
REFERENCES:
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5488730 (1996-01-01), Brown, III et al.
patent: 5497499 (1996-03-01), Garg et al.
patent: 5502827 (1996-03-01), Yoshida
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5559977 (1996-09-01), Avnon et al.
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5630157 (1997-05-01), Dwyer, III
patent: 5655096 (1997-08-01), Branigin
patent: 5666506 (1997-09-01), Hesson et al.
patent: 5673426 (1997-09-01), Shen et al.
patent: 5784588 (1998-07-01), Leung
patent: 5790827 (1998-08-01), Leung
patent: 5884057 (1999-03-01), Blomgren et al.
patent: 5887185 (1999-03-01), Lynch
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5933618 (1999-08-01), Tran et al.
patent: 5991884 (1999-11-01), Lin et al.
patent: 6076153 (2000-06-01), Grochowski et al.
patent: 6195744 (2001-02-01), Favor et al.
patent: 6219796 (2001-04-01), Bartley
patent: 6282663 (2001-08-01), Khazam
patent: 2 339 312 (2000-01-01), None
Patterson and Hennessy, “Computer Architecture: A Quantitative Approach,” Second Edition, Morgan Kaufmann Publishers, Inc., 1996, pp. 230 & 242-251.
Johnson, Mike. Superscalar Microprocessor Design. Prentice Hall, 1991. p. 18.
Patterson and Hennessy. Computer Architecture, A Quantitative Approach. Morgan Kauffman Publishing, Inc. 1996. pp. 180-183, 230, 242-251.
Hennessy, John L. and David A. Patterson. Computer Architecture: A Quantitative Approach. Morgan: 1996. p. 183.
Patterson and Hennessy, “Computer Architecture: A Quantitative Approach,” Morgan Kaufmann Publishers, Inc., 1990, pp. 291-299.
Patterson and Hennessy, “Computer Architecture: A Quantitative Approach,” Second Edition, Morgan Kaufmann Publishers, Inc., 1990, 1996, pp. 242-251.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum 2000, Jun. 13, 2000, 15 pages.
Jim Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
Tom R. Halfhill, “SiByte Reveals 64-Bit Core For NPUs; Independent MIPS64 Design Combines Low Power, High Performance,” Microdesign Resources, Jun. 2000, Microprocessor Report, 4 pages.
SiByte, Letter from Anu Sundaresan, May 18, 2000, 1 page.
Kruckemyer David A.
Rogenmoser Robert
Yeh Tse-Yu
Chan Eddie
Garlick & Harrison & Markison
Li Aimee J
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