Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2005-05-10
2005-05-10
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S216000
Reexamination Certificate
active
06892294
ABSTRACT:
A find-instructions-and-allocate-ports (FIAP) circuit and method are provided for quickly and efficiently locating one or more instructions that are ready for execution during a launch cycle in an out of order processor and allocating one or more ports associated with one or more execution resources to such ready instructions during the launch cycle. In architecture, the processor includes an instruction reordering mechanism, for example, a queue, having a plurality of slots for temporarily storing a plurality of respective instructions. Instructions can be executed in an out of order sequence from the queue. Each slot is provided with the FIAP circuit for causing and preventing launching, when appropriate, of their respective instruction. A plurality of signals is propagated successively through the FIAP circuits of the queue that causes the queue to launch a predefined plurality of the instructions, which corresponds to a predefined plurality of ports associated with the one or more execution resources. As propagation of the set of signals occurs through each slot, the set of signals indicates to the slot when and which of the one or more ports are available for each said instruction and when none of the ports are available.
REFERENCES:
patent: 5748934 (1998-05-01), Lesartre et al.
patent: 5758178 (1998-05-01), Lesartre
patent: 5761474 (1998-06-01), Lesartre et al.
patent: 5761713 (1998-06-01), Lesartre
patent: 5796975 (1998-08-01), Lesartre et al.
patent: 5796997 (1998-08-01), Lesartre et al.
patent: 5799167 (1998-08-01), Lesartre
patent: 5809275 (1998-09-01), Lesartre
patent: 5838942 (1998-11-01), Lesartre
patent: 5875340 (1999-02-01), Quarnstrom et al.
patent: 6289437 (2001-09-01), Eisen et al.
patent: 6308260 (2001-10-01), Le et al.
Microsoft Computer Dictionary, 1999, Microsoft Press, Fourth Edition, p. 32.
Chan Eddie
Harkness Charles
Hewlett--Packard Development Company, L.P.
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