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Inter-cache protocol for improved WEB performance

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Inter-frame texel cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interconnect transaction translation technique

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interface queue with bypassing capability for main storage unit

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interleave pre-checking in front of shared caches with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interleaved n-way set-associative external cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interleaving apparatus and deinterleaving apparatus

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interleaving memory in distributed vector architecture multiproc

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Internal evict with external request

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Internal processor buffering for implicit writebacks

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Internally cached static random access memory architecture

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interpolation looping of audio samples in cache connected to sys

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interpolation looping of prioritized audio samples in cache...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Intervention ordering in a multiprocessor system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Invalid write recovery apparatus and method within cache memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Invalidating cached data using secondary keys

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Invalidating multiple address cache entries

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Invalidating translation lookaside buffer entries in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Invalidation bus optimization for multiprocessors using director

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Invalidation of instruction cache line during reset handling

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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