Internal processor buffering for implicit writebacks

Details Internal processor buffering for implicit writebacks Internal processor buffering for implicit writebacks

1999-06-16

2004-06-01

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S118000, C711S143000, C711S146000, C711S154000

Reexamination Certificate

active

06745298

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to computers in general. In particular, the invention relates to a method and apparatus for performing implicit writebacks in a computer system.
BACKGROUND OF THE INVENTION
In a shared memory multiprocessor system, data necessary for one processor is often present in a cache of another processor. It is more efficient to retrieve such data from the cache rather than memory. Furthermore, the system must ensure that a request for data (e.g., by a processor or input/output device) is answered with the most current version of the data available. Therefore, the system processes a request for data by first attempting to retrieve the requested data from a processor's internal cache before going to main memory.
In conventional multiprocessor systems, a request for data is originated by a first processor. The other processors detect the data request and ascertain whether they have the requested data in one of their internal caches (“snoop phase”). If the requested data is present, the processor must provide the requested data on a bus for transport to the first processor (“data phase”). This entire process is typically governed by a particular bus protocol for the system, and is generally referred to as an “implicit writeback” scheme.
Conventional implicit writeback schemes, however, may be less than satisfactory for a number of reasons. For example, if the requested data for a data request from a first processor is found within a second processor's internal cache, the cache system for the second processor must determine whether the data request is at the top of a request queue before it can start reading out the data from the cache. The request queue maintains a record of the transactions occurring on the bus, and determines the order in which a particular transaction (e.g., data request) can be performed. If the data request is not at the top of the request queue, retrieval of the requested data from the cache must wait until the data request reaches the top of the request queue. This introduces unnecessary delay into the data phase, especially given the number of processing cycles it can take to actually retrieve the requested data from the second processor's internal cache (e.g., an L2 cache). Retrieval of data from the second processor's internal cache can be time consuming for a number of reasons, such as competing demands for data within the internal cache from the second processor itself. Moreover, if another data request comes in behind the waiting data request, the implicit writeback process for the other data request cannot begin until the waiting data request is completed.
In view of the foregoing, it can be appreciated that a substantial need exists for a method and apparatus that solves the above-discussed problems.
SUMMARY OF THE INVENTION
One embodiment of the invention comprises a method and apparatus for processing data. A request for data is received from a bus. A determination is made as to whether a cache contains the data. The data is placed in a buffer. A determination is made as to whether the bus can receive the data. The data is sent to the bus.


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