Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-12-10
1999-06-15
Shah, Alpesh M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395393, 711157, G06F 1576
Patent
active
059130695
ABSTRACT:
A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form an architectural vector register, which are references by vector applications. Memories from nodes together form an aggregate memory. The vector applications load memory vector elements from the memories to the physical vector registers, and store physical vector elements from the physical vector registers to the memories. The memory vector elements are interleaved among the memories of the nodes to reduce inter-node traffic during the loads and the stores.
REFERENCES:
patent: 4771380 (1988-09-01), Kris
patent: 4884190 (1989-11-01), Ngai et al.
patent: 5598574 (1997-01-01), Yoshinaga et al.
patent: 5625834 (1997-04-01), Nishikawa
patent: 5659706 (1997-08-01), Beard et al.
patent: 5669013 (1997-09-01), Watanabe et al.
patent: 5732251 (1998-03-01), Bartkowiak
patent: 5805875 (1998-09-01), Asanovic
patent: 5809552 (1998-09-01), Kuroiwa et al.
Kaxiras Stefanos
Sugumar Rabin A.
Cray Research Inc.
Shah Alpesh M.
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