Internally cached static random access memory architecture

Details Internally cached static random access memory architecture Internally cached static random access memory architecture

1995-11-17

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, G06F 1208

Patent

active

058359419

ABSTRACT:
A circuit for internally caching a memory device having a main memory is comprised of a cache memory of smaller size than the main memory for storing certain of the same data stored in the main memory. A tag memory is provided for mapping the information stored in the cache memory. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom. The cache memory, tag memory, and logic circuit are carried internally in the memory device.

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