Unbalanced inclusive tags
Unified memory system architecture including cache and...
Unified multilevel memory system architecture which supports...
Updating an invalid coherency state in response to snooping...
Updating remote locked cache
Upgradeable cache circuit using high speed multiplexer
Upgradeable cache circuit using high speed multiplexer
Upgradeable cache circuit using high speed multiplexer
Upgrading of snooper cache state mechanism for system bus...
Use of a cache coherency mechanism as a doorbell indicator...
Use of a context identifier in a cache memory
Use of a media cache for subsequent copying acceleration
Use of a translation cacheable flag for physical address...
Use of non-count data and index hashing to reduce false hits...
User programmable interrupt mask with timeout for enhanced resou
User-based selective cache content replacement technique
User-prioritized cache replacement
Using an L2 directory to facilitate speculative loads in a...
Using feedback to determine the size of an object cache
Using hardware counters to estimate cache warmth for...