Interleave pre-checking in front of shared caches with...

Details Interleave pre-checking in front of shared caches with... Interleave pre-checking in front of shared caches with...

2007-02-06

2007-02-06

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S127000, C711S129000, C711S152000, C711S150000

Reexamination Certificate

active

10896500

ABSTRACT:
The invention relates to a method and respective system for accessing a cache memory in a computer system, wherein the cache memory is split up in at least two segments, wherein the cache memory is accessed by a plurality of competing cache memory requests via a number of commonly used input registers, wherein a cache segment model is utilized for reflecting the cache use by said competing requests, wherein cache memory requests are processed by a processing pipe and wherein each cache-request, before entering the processing pipe, is checked whether the segments of the cache memory are available at the cycle it needs, wherein said memory comprises the steps of:a) marking a segment model cell as busy with storing, if a store-request targeting to a cache segment corresponding to said model cell has received pipe access,b) blocking off from pipe access a fetch-request targeting to a segment model cell, which is marked busy with a store operation; andc) blocking off any store-request from pipe access, if at least one fetch request, which was blocked off from pipe access according to step b), is waiting for pipe access.

REFERENCES:
patent: 4149245 (1979-04-01), Gannon et al.
patent: 5559986 (1996-09-01), Alpert et al.
patent: 6081872 (2000-06-01), Matick et al.
patent: 6154814 (2000-11-01), Uesugi

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