Interleaved n-way set-associative external cache

Details Interleaved n-way set-associative external cache Interleaved n-way set-associative external cache

2002-04-22

2004-12-14

Vital, Pierre M. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S127000, C711S133000

Reexamination Certificate

active

06832294

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to memory architectures for computer systems and, more particularly, to high performance cache memories for use with computer processors.
2. Description of the Related Art
Computer processors have attained widespread use throughout many industries. A typical goal of many processors is to process information quickly. Processors often take many clock cycles to access data that is stored in a main memory located external to the processor. Not only do these external memory accesses require a significant amount of time, these accesses also consume a significant amount of power. Cache memories have often been used to enhance computer system performance by providing a relatively small, high speed memory (or cache) for storing instructions and data that have recently been accessed by the processor.
SUMMARY OF THE INVENTION
A method, cache system, and cache controller are presented. An n-way interleaved set-associative external cache utilizes standard burst memory devices such as DDR (double data rate) memory devices. The interleaved set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags. The contents of the memory level device locations associated with each tag are stored in an alternating pattern in contiguous memory locations.
A method for storing information in a cache comprises storing a first tag data in one of a plurality of n contiguous storage locations in a memory device, wherein the first tag data is associated with a first of n locations in a memory level device. The method further comprises storing a second tag data in another one of the plurality of n contiguous storage locations in the memory device, wherein the second tag data is associated with a second one of the n locations in the memory level device. The method further comprises storing the contents of the first memory level device location in a subset of a plurality of m contiguous storage locations in the memory device, wherein the plurality of m contiguous storage locations follow the n contiguous storage locations in a contiguous relationship within the memory device, wherein the contiguous subset comprises q of the m storage locations, where m
=q. The method further comprises storing the contents of the second memory level device location in another subset of the plurality of m contiguous storage locations in the memory device, wherein the other contiguous subset comprises q of the m storage locations, wherein m
=q. The contents of the first memory level device location and the contents of the second memory level device location are stored in an interleaved relationship with each other such that portions of the first contents and second contents occupy alternating ones of the plurality of m storage locations.
A cache system is also provided. The cache system includes a memory device and logic that performs the method discussed above. A cache controller is also provided. The cache controller comprises logic that performs the method discussed above.


REFERENCES:
patent: 5893146 (1999-04-01), Pickett
patent: 6226707 (2001-05-01), Mattela et al.

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