Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-11-12
1998-05-05
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711135, G06F 1212
Patent
active
057490945
ABSTRACT:
A data processing system is described having a central processing unit (CPU) 4, a memory management unit (MMU) 6 and a cache memory 8. The CPU 4 makes cache writes in the same clock cycle that the data is output from the CPU 4. In a following clock cycle, the MMU 6 produces a signal IC indicating whether that storage operation was invalid. If the storage operation was invalid, then a flag associated with a cache storage line storing a plurality of output data words is set to indicate such invalid storage.
REFERENCES:
patent: 5226133 (1993-07-01), Taylor et al.
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5408636 (1995-04-01), Santeler et al.
Intel, "Intel DX4 Processor Data Book," Feb. 1994, pp. 8-22 & 8-24, 6-1 to 6-2.
Fu et al., "Performance and Microarchitecture of the i486.TM. Processor", 1989, IEEE, pp. 182-187.
Miyake et al., "A 40 MIPS (Peak) 64-bit Microprocessor with One-Clock Physical Cache Load/Store", 1990, IEEE, pp. 42-43, 261.
Safai, M., and Stodieck, R., "Complete High-Performance Cache System for the 80386", Microprocessors and Microsystems, vol. 14, No. 10, Dec. 1990, pp. 664-674.
Advanced Risc Machines Limited
Chan Eddie P.
Ellis Kevin L.
LandOfFree
Invalid write recovery apparatus and method within cache memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Invalid write recovery apparatus and method within cache memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Invalid write recovery apparatus and method within cache memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-71747